This invention relates to latch control circuitry. More specifically, this invention relates to a particular latch control circuit for communicating between clock domains that have clocks of the same frequency, but which may be out of phase.
Advances in integrated circuit fabrication technology continue to lead to systems with higher clock speeds and larger gate counts. As a consequence, wiring delays can be comparable to or greater than the clock period and the difference in delays of the clock signal to different points in the system, commonly referred to as xe2x80x9cclock skew,xe2x80x9d limits the speed at which large synchronous circuits can operate. To simplify the design process, circuit designers typically partition large circuits into several smaller circuits having their own xe2x80x9cclock domainxe2x80x9d. Often all of these clock domains receive their clock from a common clock generator so that the clock frequency is the same for all domains. However, because distribution delays of the clock vary from one domain to the next, the phase difference between different clock domains can be significant and difficult to determine.
One method of overcoming phase uncertainty between different clock domains is to use a source synchronous design, which utilizes a first-in-first-out (FIFO) buffer for communication between clock domains. Two common types of FIFOs used in such a design are the pointer FIFO and the ripple FIFO. The pointer FIFO typically comprises two counters and a dual-port register file that is read from and written to according to read and write pointers derived from the counters. While these are commonly used, they require a substantial amount of support and control circuitry, including address decoder circuitry and circuitry to implement the read and write pointer functions. The ripple FIFO comprises a latch to hold data and control circuitry to regulate the transfer of data between stages. A state bit in the control circuitry marks a stage as either xe2x80x9cemptyxe2x80x9d or xe2x80x9cfall.xe2x80x9d When stage i is full and stage i+1 is empty, the control circuitry of stages i and i+1 enable latch i+1 to acquire a data item from stage i. Along with this data transfer, the state bit of stage i moves to an empty state, and the state bit of stage i+1 moves to a full state.
In an exemplary embodiment of the present invention, a latch control circuit for overcoming phase uncertainty between crossing clock domains is provided. The latch control circuit includes an interface and control circuit for controlling the communication of data between the two domains.
In a first aspect of the invention, a latch control circuit for conveying data from a clock domain of a transmitter to a clock domain of a receiver is disclosed. The latch control circuit comprises: a data path having a transmitter latch controlled by a transmitter clock in a first clock domain, a receiver latch controlled by a receiver clock in a second clock domain, and an intermediate latch coupled between the transmitter and receiver latches; an interface and control circuit coupled between the transmitter clock and the receiver clock, the interface and control circuit including a clock generator having inputs controlled by delayed versions of the transmitter and receiver clocks and an output coupled to the intermediate latch for controlling the conveyance of a data item from the transmitter latch to the receiver latch.
In a second aspect of the invention, clock edge-to-level converters are included within the latch control circuit described in reference to the first aspect of the invention. A transmitter clock edge-to-level converter includes an input coupled to the transmitter clock, via a first delay that is greater than or equal to zero, and an output coupled to a first end of a first keeper circuit. The transmitter clock edge-to-level converter is operable to convert an edge of the transmitter clock to a logic level. A receiver clock edge-to-level converter is also included and has an input coupled to the receiver clock, via a second delay that is greater than or equal to zero, and an output coupled to a first end of a second keeper circuit. The receiver clock edge-to-level converter is operable to convert an edge of the receiver clock to a logic level. Further, the clock generator is configured to send a clock signal to the intermediate latch when the inverse of the logic level is asserted at first and second inputs of the clock generator.
In a third aspect of the invention, the clock generator described in reference to the second aspect of the invention, comprises a NAND logic gate having a first input coupled to the second end of the first keeper circuit, a second input coupled to the second end of the second keeper circuit and an output; and an inverter having an input coupled to the output of the NAND gate and an output that provides the clock signal to the intermediate latch.
In a fourth aspect of the invention, the latch control circuit, described in reference to the first aspect of the invention, includes static initialization circuitry comprising a first latch having a clock input coupled to the inverse of the transmitter clock, via a first delay that is greater than or equal to zero, an input selectively coupled to a transmitter reset signal and an output coupled to the input of the transmitter clock edge-to-level converter; a second latch having a clock input coupled to the inverse of the receiver clock, an input, and an output coupled to the input of the receiver clock edge-to-level converter; and a third latch having a clock input coupled to the receiver clock, an input selectively coupled to a receiver reset signal and an output coupled to the input of the second latch.
In a fifth aspect of the invention, a latch control circuit including dynamic initialization circuitry is disclosed.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.